This invention relates, in general, to integrated circuit structures and fabrication methods and, in particular, to techniques using the etching of porous silicon areas followed by a metal-lined dielectric backfill to provide isolation for circuit components, including isolation of functionally distinct circuit components from other functionally distinct circuit components and the semiconductor substrate to minimize parasitic AC coupling.
Integrated circuits have been designed to ever-smaller geometries, and required to carry signals of ever-increasing frequencies. As integrated circuit components and signal lines are placed more closely together, and as the frequencies at which the components and signal lines operate are increased to radio frequencies (RF), the components and signal lines strongly couple electromagnetically to the substrate. This results in low power efficiency and restricts the maximum frequency at which the integrated circuit can function.
Previous methods have attempted to overcome the problem of coupling by increasing space between radiant components and receptive components, which results in larger die area and increased design costs. Other previous techniques have boosted the voltage levels of low voltage signals requiring a high degree of isolation resulting in lower power efficiency and relatively high power emissions that may couple undesirably with other signals.
Previous designs have used trenches to isolate components from a substrate; but such attempts typically fail to yield the 100 decibels (dB) of isolation necessary to integrate systems comprising functionally distinct circuits comprising mixed signal devices (such as base band, phase-locked-loop, or voltage controlled oscillators) or functionally distinct circuits requiring different power levels (such as transmitter or receiver) on the same substrate.
Even with removing or changing the substrate, or isolating the component from the substrate, the degrees of isolation necessary to integrate many RF systems on a single chip have not been achieved. Thus, commercially viable isolation of RF components from the substrate is now needed.
Therefore, a method for fabricating an integrated circuit having active components, high frequency conductors and isolation regions on a substrate is now needed; providing enhanced design performance while overcoming the aforementioned limitations of conventional methods.
The present invention provides integrated circuit structures and fabrication methods, including techniques using the etching of porous silicon areas and dielectric backfill to provide isolation for circuit components. The present invention provides for isolation of circuit components, including decoupling of RF passive components such as transmission lines on a circuit structure from a semiconductor substrate, to minimize parasitics. The present invention provides a method of fabricating an integrated circuit having active components, conductors and isolation regions on a substrate.
An embodiment of the present invention comprises patterning and etching a portion of at least one of the isolation regions to expose a first area of the substrate; depositing a layer of silicon carbide (or other material resistant to a porous silicon formation process) over the substrate including the first area; patterning and etching the silicon carbide mask layer to expose a second area of the substrate within the first area; anodizing the substrate to produce porous silicon so that the porous silicon lies in an area underneath the second area and extends only part way to the bottom surface of the substrate; etching the porous silicon to form a void; removing the silicon carbide mask layer to expose the isolation region; depositing a conductive layer over all exposed surfaces of the substrate comprising the void and the isolation region; depositing a dielectric layer over the conductive layer wherein the dielectric layer extends at least to the height of the isolation region; polishing the surface of the dielectric layer until the surface is planar and the top surface of the isolation region is exposed; and forming at least one patterned conductive layer over the surface of the dielectric layer that is coplanar with the surface of the isolation region.
In another embodiment of the present invention, the fabrication of an RF integrated circuit having active components, high frequency conductors and isolation regions on a substrate, comprises the forming of isolation regions in a substrate; forming active components in said substrate; patterning at least one of the isolation regions to expose a first area of said substrate; etching away some of the field oxide; forming a patterned masking layer of silicon carbide over said substrate, preferably by Plasma Enhanced Chemical Vapor Deposition (PECVD); patterning and etching the silicon carbide layer to expose a second area of the substrate within the first area; anodizing the porous silicon region; exposing the porous silicon from the backside, e.g., by back grinding; removing the porous silicon from backside; coating the walls of the void left by the removal of the porous silicon with a metal isolation layer, and spin-coating on glass to fill voids left by the removal.
The present invention may be used to form a structure that separates functionally distinct circuits on the substrate by traversing a boundary that fully segregates on the substrate the areas of each functionally distinct circuit.